
// Purpose:




// set FPGA test muxes

WA8EWD2B

WA8FWD1F

WA1FWDDC




// set all other registers

WA20WD01

WA21WD00

WA22WD00

WA23WD02

WA24WD02

WA25WD01

WA26WD01

WA27WD02

WA28WD00




WA80WD15

WA81WD01

WA82WD01

WA83WDBE

WA84WDFC

WA85WD2A

WA86WDCB

WA87WDC8

WA88WD00

WA89WD9D

WA8AWDA4

WA8BWD79

WA8CWD00

WA8DWDCC




WA0FWDB0

WA14WD0B




//Stop all things

//Turn off SMIA decoder

WA80WD05

WA83WD3E

WA10WD01

WA80WD14

//Disable the loop controller

WA11WD20

//Disable the list controller

WA1DWD00

//make sure no data is writen into instruction memory

WA00WD98

// make sure no spi signal goes out

WA00WD88

// set to direct sending of spi signals




////////////////////////

//SPI SETTINGS

////////////////////////

//set up command settings

WA03WD70

// Set SPI master settings

WA04WD10

//Set length of direct sent spi signals

WA05WD01

//Set which target is the device for direct spi sending

WA06WD31

//set spi clock divider




////////////////////////////////////////////////////////////////////////////////////////////////




WA00WD88

// set for direct spi operation to CHIP from GUI




//Init Registers


//Bank: 0, Register: 128, SetValue: 0
WA00WD88   //Reset
WA01WD00   //Data & Address
WA02WD80   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 129, SetValue: 1
WA00WD88   //Reset
WA01WD01   //Data & Address
WA02WD81   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 130, SetValue: 3
WA00WD88   //Reset
WA01WD03   //Data & Address
WA02WD82   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 131, SetValue: 5
WA00WD88   //Reset
WA01WD05   //Data & Address
WA02WD83   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 132, SetValue: 10
WA00WD88   //Reset
WA01WD0A   //Data & Address
WA02WD84   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 133, SetValue: 8
WA00WD88   //Reset
WA01WD08   //Data & Address
WA02WD85   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 134, SetValue: 0
WA00WD88   //Reset
WA01WD00   //Data & Address
WA02WD86   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 135, SetValue: 7
WA00WD88   //Reset
WA01WD07   //Data & Address
WA02WD87   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 137, SetValue: 7
WA00WD88   //Reset
WA01WD07   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 138, SetValue: 63
WA00WD88   //Reset
WA01WD3F   //Data & Address
WA02WD8A   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 139, SetValue: 36
WA00WD88   //Reset
WA01WD24   //Data & Address
WA02WD8B   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 140, SetValue: 35
WA00WD88   //Reset
WA01WD23   //Data & Address
WA02WD8C   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 141, SetValue: 39
WA00WD88   //Reset
WA01WD27   //Data & Address
WA02WD8D   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 142, SetValue: 39
WA00WD88   //Reset
WA01WD27   //Data & Address
WA02WD8E   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Bank: 0, Register: 143, SetValue: 0
WA00WD88   //Reset
WA01WD00   //Data & Address
WA02WD8F   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Init Array (global setting of SRAM in array)



//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset





//Bank: 0, Register: 136, SetValue: 160
WA00WD88   //Reset
WA01WDA0   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

// set global arrray threshold


//Bank: 0, Register: 137, SetValue: 128
WA00WD88   //Reset
WA01WD80   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 164
WA00WD88   //Reset
WA01WDA4   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 160
WA00WD88   //Reset
WA01WDA0   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset





//Bank: 0, Register: 137, SetValue: 130
WA00WD88   //Reset
WA01WD82   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 168
WA00WD88   //Reset
WA01WDA8   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 160
WA00WD88   //Reset
WA01WDA0   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset





//Bank: 0, Register: 137, SetValue: 6
WA00WD88   //Reset
WA01WD06   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 162
WA00WD88   //Reset
WA01WDA2   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 160
WA00WD88   //Reset
WA01WDA0   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//Init Test sub array (set delay, thereshold, vtest, and ATP for 3x3 array)

//RUN_SCRIPT



//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

// vtest goes to pixel 0,0

//SET_CHIP_PULSE


//Bank: 0, Register: 1, SetValue: 1
WA00WD88   //Reset
WA01WD01   //Data & Address
WA02WD01   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE

//SET_CHIP_PULSE





//Bank: 0, Register: 137, SetValue: 7
WA00WD88   //Reset
WA01WD07   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 34
WA00WD88   //Reset
WA01WD22   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 137, SetValue: 7
WA00WD88   //Reset
WA01WD07   //Data & Address
WA02WD89   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 36
WA00WD88   //Reset
WA01WD24   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset


//Bank: 0, Register: 136, SetValue: 32
WA00WD88   //Reset
WA01WD20   //Data & Address
WA02WD88   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

//SET_CHIP_PULSE

//SET_CHIP_SIGNAL

//SET_CHIP_SIGNAL




//RUN_SCRIPT


// set up

WA2AWDA0

WA2AWDA0

WA2AWDA0

WA2AWDA0

// **ERROR** Can't Find Signal: queue2_sel_load_mempadd

// **ERROR** Can't Find Signal: queue2_sel_load_mempdata




//set min memory

WA29WD00

WA2AWDA4

WA2AWDE4

WA2AWDA4

WA2AWDA0




//set max memory

WA29WD09

WA2AWDA2

WA2AWDE2

WA2AWDA2

WA2AWDA0




//first packet

WA29WD00

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 1

WA29WD01

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 1

WA29WD01

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//second packet

WA29WD01

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 0

WA29WD00

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 1

WA29WD01

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//third packet

WA29WD02

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 2

WA29WD02

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 1

WA29WD01

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//forth packet

WA29WD03

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 1

WA29WD01

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 0

WA29WD00

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//fith packet

WA29WD04

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 1

WA29WD01

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 2

WA29WD02

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//sixth packet

WA29WD05

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 0

WA29WD00

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 0

WA29WD00

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//seventh packet

WA29WD06

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 0

WA29WD00

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 2

WA29WD02

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//eight packet

WA29WD07

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 2

WA29WD02

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 0

WA29WD00

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//nineth packet

WA29WD08

WA2AWDA1

WA2AWDE1

WA2AWDA1

WA2AWDA0

//Select row 2

WA29WD02

WA2AWDB0

WA2AWDF0

WA2AWDB0

WA2AWDA0

//Select column 2

WA29WD02

WA2AWDA8

WA2AWDE8

WA2AWDA8

WA2AWDA0




//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT

//RUN_SCRIPT





//Bank: 0, Register: 134, SetValue: 2
WA00WD88   //Reset
WA01WD02   //Data & Address
WA02WD86   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset

WAIT00010


//Bank: 0, Register: 134, SetValue: 0
WA00WD88   //Reset
WA01WD00   //Data & Address
WA02WD86   //Data & Address
WA00WD89   //Trigger
WA00WD88   //Reset







// Set for chip spi operation from command controller in FPGA




//Loop: 0 - PrepareReadHitLocation
WA12WD01   //Loop Number
WA13WD00   //Loop Number
WA11WD01   //Trigger
WA11WD00   //Reset
WA12WD45   //Loop Time
WA13WD00   //Loop Time
WA11WD02   //Trigger
WA11WD00   //Reset
WA12WD00   //Number of Loops
WA13WD00   //Number of Loops
WA11WD04   //Trigger
WA11WD00   //Reset
WA12WD01   //First Instruction Mem Index
WA13WD00   //First Instruction Mem Index
WA11WD08   //Trigger
WA11WD00   //Reset

//Loop: 1 - ReadoutPixels
WA12WD02   //Loop Number
WA13WD00   //Loop Number
WA11WD11   //Trigger
WA11WD10   //Reset
WA12WDBA   //Loop Time
WA13WD00   //Loop Time
WA11WD12   //Trigger
WA11WD10   //Reset
WA12WD08   //Number of Loops
WA13WD00   //Number of Loops
WA11WD14   //Trigger
WA11WD10   //Reset
WA12WD05   //First Instruction Mem Index
WA13WD00   //First Instruction Mem Index
WA11WD18   //Trigger
WA11WD10   //Reset

//Loop: 2 - Cleanup
WA12WD00   //Loop Number
WA13WD00   //Loop Number
WA11WD21   //Trigger
WA11WD20   //Reset
WA12WD77   //Loop Time
WA13WD00   //Loop Time
WA11WD22   //Trigger
WA11WD20   //Reset
WA12WD00   //Number of Loops
WA13WD00   //Number of Loops
WA11WD24   //Trigger
WA11WD20   //Reset
WA12WD0E   //First Instruction Mem Index
WA13WD00   //First Instruction Mem Index
WA11WD28   //Trigger
WA11WD20   //Reset


//Loop: 0, Inst: 0 - DisableHitParLoad
WA15WD21   //Reg Address & Value
WA16WD88   //Reg Address & Value
WA17WD11   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD02   //Inst Next Instruction Address
WA1CWD10   //Inst Queues & Flags
WA1EWD01   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 0, Inst: 1 - ReadSPI1
WA15WDFF   //Reg Address & Value
WA16WDFF   //Reg Address & Value
WA17WD22   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD03   //Inst Next Instruction Address
WA1CWD10   //Inst Queues & Flags
WA1EWD02   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 0, Inst: 2 - ReadSPI2
WA15WDFF   //Reg Address & Value
WA16WDFF   //Reg Address & Value
WA17WD33   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD04   //Inst Next Instruction Address
WA1CWD10   //Inst Queues & Flags
WA1EWD03   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 0, Inst: 3 - ReadSPI3
WA15WDFF   //Reg Address & Value
WA16WDFF   //Reg Address & Value
WA17WD44   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD00   //Inst Next Instruction Address
WA1CWD14   //Inst Queues & Flags
WA1EWD04   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 0 - AddressPixel
WA15WD01   //Reg Address & Value
WA16WD01   //Reg Address & Value
WA17WD11   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD06   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD05   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 1 - Phase1
WA15WD02   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD22   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD07   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD06   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 2 - Phase2
WA15WD07   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD33   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD08   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD07   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 3 - Phase3
WA15WD0F   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD44   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD09   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD08   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 4 - Phase 4
WA15WD1F   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD55   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD0A   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD09   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 5 - Phase 4 reset
WA15WD0F   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD66   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD0B   //Inst Next Instruction Address
WA1CWD40   //Inst Queues & Flags
WA1EWD0A   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 6 - Phase 5
WA15WD2F   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD77   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD0C   //Inst Next Instruction Address
WA1CWD60   //Inst Queues & Flags
WA1EWD0B   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 7 - Phase 6
WA15WD6F   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WD98   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD0D   //Inst Next Instruction Address
WA1CWD60   //Inst Queues & Flags
WA1EWD0C   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 1, Inst: 8 - Reset Phase
WA15WD00   //Reg Address & Value
WA16WD8F   //Reg Address & Value
WA17WDB9   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD00   //Inst Next Instruction Address
WA1CWD44   //Inst Queues & Flags
WA1EWD0D   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 0 - AddressQueueClean
WA15WDFF   //Reg Address & Value
WA16WDFF   //Reg Address & Value
WA17WD21   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD0F   //Inst Next Instruction Address
WA1CWD61   //Inst Queues & Flags
WA1EWD0E   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 1 - QueueCommand
WA15WDFF   //Reg Address & Value
WA16WDFF   //Reg Address & Value
WA17WD32   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD10   //Inst Next Instruction Address
WA1CWD00   //Inst Queues & Flags
WA1EWD0F   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 2 - GhitReset
WA15WD02   //Reg Address & Value
WA16WD86   //Reg Address & Value
WA17WD43   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD11   //Inst Next Instruction Address
WA1CWD00   //Inst Queues & Flags
WA1EWD10   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 3 - Access Out of Range
WA15WD21   //Reg Address & Value
WA16WD20   //Reg Address & Value
WA17WD54   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD12   //Inst Next Instruction Address
WA1CWD00   //Inst Queues & Flags
WA1EWD11   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 4 - ReleaseGhitReset
WA15WD00   //Reg Address & Value
WA16WD86   //Reg Address & Value
WA17WD65   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD13   //Inst Next Instruction Address
WA1CWD00   //Inst Queues & Flags
WA1EWD12   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE

//Loop: 2, Inst: 5 - EnablePLoadAndHitRecord
WA15WD20   //Reg Address & Value
WA16WD88   //Reg Address & Value
WA17WD76   //Inst TimeStamp
WA18WD00   //Inst TimeStamp
WA19WD10   //Inst Length
WA1AWD01   //Inst Target Devices
WA1BWD00   //Inst Next Instruction Address
WA1CWD80   //Inst Queues & Flags
WA1EWD13   //Inst Address
WA1DWD01   //Trigger WE
WA1DWD00   //Reset WE




// load command timing

//Send timing

WA00WD98




// Run

WA11WD20

WA10WD09

WA12WD00

//Reset List controller

WA00WD98

//Reset Direct Send

//SET_SYS_SIGNAL

WA12WD01

//let List or Loop controller run

WA80WD00

WA80WD15










WA80WD05

WA80WD14

WA80WD15

WA83WDBE

WA80WD15