/* ********************************************************************************************************* * PXA 270-520-10 Microprocessor * Board Support Package * * (c) Copyright 2004, Micrium, Weston, FL * All Rights Reserved * * Logic Zoom SDK Card Engine and Kit * * File : BSP.H * By : Jean J. Labrosse * Modified by: Lance Simms * Lawrence Livermore National Labs * * Modifications have been made for PXA270 specific registers. Interrupt handling is * still a work in progress. * ********************************************************************************************************* */ /* ********************************************************************************************************* * ADDRESSES ********************************************************************************************************* */ //INTERRUPT STATUS AND CONTROL REGISTERS #define INT_IRQ_CONTROLLER_ADDR (*(INT32U *) 0x40D00000L) //Contains the IRQ source flags (p. 1106 in PXA270 Manual) #define INT_IRQ2_CONTROLLER_ADDR (*(INT32U *) 0x40D000ACL) //Contains the IRQ source flags for QCI #define INT_MASK_ADDR (*(INT32U *) 0x40D00004L) //Register for masking interrupts (p.1112 in PXA270 Manual) #define INT_MASK2_ADDR (*(INT32U *) 0x40D000A0L) //Register for masking 2nd interrupts (QCI) #define INT_LEVEL_REG_ADDR (*(INT32U *) 0x40D00008L) //Register that determines whether source generates FIQ or IRQ #define INT_FIQ_CONTROLLER_ADDR (*(INT32U *) 0x40D0000CL) //Register that contains the FIQ source flags (p. 1106 in PXA270 Manual) #define INT_IRQ_ICPR_REG_ADDR (*(INT32U *) 0x40D00010L) //Contains the status of IRQs and FIQs for each peripheral //GPIO PIN REGISTERS #define GPIO_PIN_DIRECTION0_REG_ADDR (*(INT32U *) 0x40E0000CL) //Register that determines if GPIO[0-31] are used as inputs (0) or outputs (1) #define GPIO_PIN_DIRECTION1_REG_ADDR (*(INT32U *) 0x40E00010L) //Register that determines if GPIO[32-63] are used as inputs (0) or outputs (1) #define GPIO_PIN_DIRECTION2_REG_ADDR (*(INT32U *) 0x40E00014L) //Register that determines if GPIO[64-95] are used as inputs (0) or outputs (1) #define GPIO_PIN_DIRECTION3_REG_ADDR (*(INT32U *) 0x40E0010CL) //Register that determines if GPIO[96-120] are used as inputs (0) or outputs (1) #define GPIO_PIN_OUTPUT_SET0_REG_ADDR (*(INT32U *) 0x40E00018L) //Register that sets GPIO[0-31] high with a 1 #define GPIO_PIN_OUTPUT_SET1_REG_ADDR (*(INT32U *) 0x40E0001CL) //Register that sets GPIO[32-63] high with a 1 #define GPIO_PIN_OUTPUT_SET2_REG_ADDR (*(INT32U *) 0x40E00020L) //Register that sets GPIO[64-95] high with a 1 #define GPIO_PIN_OUTPUT_SET3_REG_ADDR (*(INT32U *) 0x40E00118L) //Register that sets GPIO[96-120] high with a 1 #define GPIO_PIN_OUTPUT_CLR0_REG_ADDR (*(INT32U *) 0x40E00024L) //Register that clears GPIO[0-31] high with a 1 #define GPIO_PIN_OUTPUT_CLR1_REG_ADDR (*(INT32U *) 0x40E00028L) //Register that clears GPIO[32-63] high with a 1 #define GPIO_PIN_OUTPUT_CLR2_REG_ADDR (*(INT32U *) 0x40E0002CL) //Register that clears GPIO[64-95] high with a 1 #define GPIO_PIN_OUTPUT_CLR3_REG_ADDR (*(INT32U *) 0x40E00124L) //Register that clears GPIO[96-120] high with a 1 #define GPIO_ALT_DEF_00_15_REG_ADDR (*(INT32U *) 0x40E00054L) //Alternate definition function for GPIO[0-15] #define GPIO_ALT_DEF_16_31_REG_ADDR (*(INT32U *) 0x40E00058L) //Alternate definition function for GPIO[16-31] #define GPIO_ALT_DEF_32_47_REG_ADDR (*(INT32U *) 0x40E0005CL) //Alternate definition function for GPIO[32-48] #define GPIO_ALT_DEF_48_63_REG_ADDR (*(INT32U *) 0x40E00060L) //Alternate definition function for GPIO[48-63] #define GPIO_ALT_DEF_64_79_REG_ADDR (*(INT32U *) 0x40E00064L) //Alternate definition function for GPIO[64-79] #define GPIO_ALT_DEF_80_95_REG_ADDR (*(INT32U *) 0x40E00068L) //Alternate definition function for GPIO[80-95] #define GPIO_ALT_DEF_96_111_REG_ADDR (*(INT32U *) 0x40E0006CL) //Alternate definition function for GPIO[96-111] #define GPIO_ALT_DEF_112_120_REG_ADDR (*(INT32U *) 0x40E00070L) //Alternate definition function for GPIO[112-120] #define GPIO_PIN_RISING_EDGE0_REG_ADDR (*(INT32U *) 0x40E00030L) //Rising Edge Detection for GPIO[0-31] #define GPIO_PIN_RISING_EDGE1_REG_ADDR (*(INT32U *) 0x40E00034L) //Rising Edge Detection for GPIO[32-63] #define GPIO_PIN_RISING_EDGE2_REG_ADDR (*(INT32U *) 0x40E00038L) //Rising Edge Detection for GPIO[64-95] #define GPIO_PIN_RISING_EDGE3_REG_ADDR (*(INT32U *) 0x40E00130L) //Rising Edge Detection for GPIO[96-119] #define GPIO_PIN_FALLING_EDGE0_REG_ADDR (*(INT32U *) 0x40E0003CL) //Falling Edge Detection for GPIO[0-31] #define GPIO_PIN_FALLING_EDGE1_REG_ADDR (*(INT32U *) 0x40E00040L) //Falling Edge Detection for GPIO[32-63] #define GPIO_PIN_FALLING_EDGE2_REG_ADDR (*(INT32U *) 0x40E00044L) //Falling Edge Detection for GPIO[64-95] #define GPIO_PIN_FALLING_EDGE3_REG_ADDR (*(INT32U *) 0x40E0013CL) //Falling Edge Detection for GPIO[96-119] #define GPIO_EDGE_DETECT_STATUS1_REG_ADDR (*(INT32U *) 0x40E00048L) //Edge Detection Status Register for GPIO[0-31] #define GPIO_EDGE_DETECT_STATUS2_REG_ADDR (*(INT32U *) 0x40E0004CL) //Edge Detection Status Register for GPIO[32-63] #define GPIO_EDGE_DETECT_STATUS3_REG_ADDR (*(INT32U *) 0x40E00050L) //Edge Detection Status Register for GPIO[64-95] #define GPIO_EDGE_DETECT_STATUS4_REG_ADDR (*(INT32U *) 0x40E00148L) //Edge Detection Status Register for GPIO[96-119] //DMA REGISTERS #define DMA_DSCR_0_REG_ADDR (*(INT32U *) 0x40000000L) //DMA Control Status (DSCR) Register for Channel 0 of DMA #define DMA_DDADR_0_REG_ADDR (*(INT32U *) 0x40000200L) //DMA Descriptor (DDADR) Address Register for Channel 0 of DMA #define DMA_DSADR_0_REG_ADDR (*(INT32U *) 0x40000204L) //DMA Source (DSADR) Address Register for Channel 0 of DMA #define DMA_DTADR_0_REG_ADDR (*(INT32U *) 0x40000208L) //DMA Target (DTADR) Address Register for Channel 0 of DMA #define DMA_DCMD_0_REG_ADDR (*(INT32U *) 0x4000020CL) //DMA Command (DCMD) Address Register for Channel 0 of DMA #define DMA_QCI_DRCMR_68_REG_ADDR (*(INT32U *) 0x40001110L) //DMA Request to Channel Map (DRCMR) Register for Quick Capture Interface (map to Ch 0) #define DMA_DRQSR0_REG_ADDR (*(INT32U *) 0x400000E0L) //DMA DREQ0 Status Register #define DMA_DRQSR1_REG_ADDR (*(INT32U *) 0x400000E4L) //DMA DREQ1 Status Register #define DMA_DRQSR2_REG_ADDR (*(INT32U *) 0x400000E8L) //DMA DREQ2 Status Register #define DMA_INTERRUPT_REG_ADDR (*(INT32U *) 0x400000F0L) //DMA Interrupt Register //QUICK CAPTURE INTERFACE REGISTERS (Connected to Cypress Imager) #define QCI_CICR0_REG_ADDR (*(INT32U *) 0x50000000L) //Quick Capture Control Reg 0 (DMA, Slave Mode, Masks) #define QCI_CICR1_REG_ADDR (*(INT32U *) 0x50000004L) //Quick Capture Control Reg 1 (RGB, Data Width) #define QCI_CICR2_REG_ADDR (*(INT32U *) 0x50000008L) //Quick Capture Control Reg 2 (Pixel Counts and Wait Times) #define QCI_CICR3_REG_ADDR (*(INT32U *) 0x5000000CL) //Quick Capture Control Reg 3 (More Wait Times) #define QCI_CICR4_REG_ADDR (*(INT32U *) 0x50000010L) //Quick Capture Control Reg 4 (Frame Capture Rate and Clock Divisor) #define QCI_TIMEOUT_REG_ADDR (*(INT32U *) 0x5000001CL) //Quick Capture TimeOut Reg #define QCI_STATUS_REG_ADDR (*(INT32U *) 0x50000014L) //Quick Capture Status Reg #define QCI_FIFO_CONTROL_REG_ADDR (*(INT32U *) 0x50000018L) //Quick Capture FIFO Control Reg #define QCI_RECEIVE_BUFF0_REG_ADDR (*(INT32U *) 0x50000028L) //Quick Capture Receive Buffer Register 0 #define QCI_RECEIVE_BUFF1_REG_ADDR (*(INT32U *) 0x50000030L) //Quick Capture Receive Buffer Register 1 #define QCI_RECEIVE_BUFF2_REG_ADDR (*(INT32U *) 0x50000038L) //Quick Capture Receive Buffer Register 2 //COMPACT FLASH "REGISTERS" (Really these are combinations of address lines A0-A9 & A12) #define CF_CONFIG_OPTION_REG_ADDR (*(INT8U *) 0x14000200L) //Configuration Option Register #define CF_CARD_CONFIG_AND_STATUS_REG_ADDR (*(INT8U *) 0x14000202L) //Card configuration and status register #define CF_PINREPLACEMENT_REG_ADDR (*(INT8U *) 0x14000204L) //Pin replacement register that should have "busy" signal #define CF_SOCKET_AND_COPY_REG_ADDR (*(INT8U *) 0x14000206L) //Socket and copy register #define CF_EVEN_RD_DATA_REG_ADDR (*(INT16U *) 0x14001000L) //RD - EVEN RD DATA ; WR - EVEN WR DATA (Configured for 16 bit word) #define CF_EVEN_RD_DATA_REG_ADDR2 (*(INT8U *) 0x14001000L) //RD - EVEN RD DATA ; WR - EVEN WR DATA (Configured for 8 bit word ...not available here) #define CF_ERROR_REG_ADDR (*(INT8U *) 0x14001001L) //RD - ERROR ; WR - FEATURES #define CF_SECTOR_CNT_REG_ADDR (*(INT16U *) 0x14001002L) //RD - SECTOR CNT ; WR - SECTOR CNT #define CF_SECTOR_CNT_BYTE_REG_ADDR (*(INT8U *) 0x14001002L) //RD - SECTOR CNT ; WR - SECTOR CNT #define CF_SECTOR_NUM_REG_ADDR (*(INT8U *) 0x14001003L) //RD - SECTOR NUM ; WR - SECTOR NUM #define CF_CYL_LOW_REG_ADDR (*(INT16U *) 0x14001004L) //RD - CYLINDER LOW ; WR - CYLINDER HIGH #define CF_CYL_LOW_BYTE_REG_ADDR (*(INT8U *) 0x14001004L) //RD - CYLINDER LOW ; WR - CYLINDER HIGH #define CF_CYL_HIGH_REG_ADDR (*(INT8U *) 0x14001005L) //RD - CYLINDER HIGH ; WR - CYLINDER HIGH #define CF_SELECT_CARD_HEAD_REG_ADDR (*(INT16U *) 0x14001006L) //RD - SELECT C/H ; WR - SELECT C/H #define CF_SELECT_CARD_HEAD_BYTE_REG_ADDR (*(INT8U *) 0x14001006L) //RD - SELECT C/H ; WR - SELECT C/H #define CF_CMD_OR_STATUS_REG_ADDR (*(INT8U *) 0x14001007L) //RD - STATUS REG ; WR - COMMAND REG #define CF_ERROR_REG_ADDR2 (*(INT8U *) 0x1400100DL) //RD - ERROR ; WR - FEATURES (D15-D8 have the 8 byte code) #define CF_DEVICE_CONTROL_REG_ADDR (*(INT8U *) 0x1400100EL) //Device Control Reg that contains interrupt information #define EXPANSION_MEM_CFG_REG_ADDR (*(INT8U *) 0x48000014L) //Expansion Memory Configuration Register (p. 357 of PXA dev manual) //SERIAL PORT REGISTERS FOR FFUARTA (Full-Functional Universal Asyncrhonous Receiver/Transmitter) #define FFUARTA_TXD_REG_ADDR (*(INT8U *) 0x40100000L) //TX REGISTER FOR UARTA SERIAL PORT #define FFUARTA_RXD_REG_ADDR (*(INT8U *) 0x40100000L) //RX REGISTER FOR UARTA SERIAL PORT #define FFUARTA_DIVISOR_LBYTE_REG_ADDR (*(INT8U *) 0x40100000L) //Lower byte for divisor when setting baud rate #define FFUARTA_DIVISOR_UBYTE_REG_ADDR (*(INT8U *) 0x40100004L) //Upper byte for divisor when setting baud rate #define FFUARTA_INT_CONTROL_REG_ADDR (*(INT32U *) 0x40100004L) //Interrupt enable register for FFUART (Value is 0x41 at start-up : DMA disabled ) #define FFUARTA_INT_ID_REG_ADDR (*(INT32U *) 0x40100008L) //READ ONLY - Contains interrupt code (Value is 0xC1 at start-up : FIFO mode enabled) #define FFUARTA_FCR_REG_ADDR (*(INT32U *) 0x40100008L) //WRITE ONLY - FIFO Enable/Reset registter for FFUART #define FFUARTA_LCR_REG_ADDR (*(INT32U *) 0x4010000CL) //Line control register. Contains DLAB bit that allows setting of baud #define FFUARTA_MCR_REG_ADDR (*(INT32U *) 0x40100010L) //Modem Control Register. This has an effect on whether interrupts are enabled or not #define FFUARTA_LINE_STATUS_REG_ADDR (*(INT32U *) 0x40100014L) //Line Status Register, used to control flow to the transmit FIFO #define FFUARTA_MSR_REG_ADDR (*(INT32U *) 0x40100018L) //Modem Status Register. Contains info on the handshaking lines #define FFUARTA_SCRATCH_PAD_REG_ADDR (*(INT32U *) 0x4010001CL) //Scratch pad register. Not used on chip #define FFUARTA_INFRARED_SELELCT_REG_ADDR (*(INT32U *) 0x40100020L) //Settings for infrared control register #define FFUARTA_RX_FIFO_OCCUPANCY_REG_ADDR (*(INT32U *) 0x40100024L) //Contains the number of characters in the receive FIFO (0-63) #define FFUARTA_ABR_REG_ADDR (*(INT32U *) 0x40100028L) //Auto-Baud Rate register. Contains bits for controlling baud rate generation #define FFUARTA_ABC_REG_ADDR (*(INT32U *) 0x4010002CL) //Auto-Baud Count register. Stores number of 14.857-MHz clock cycles used for AB //SERIAL PORT REGISTERS FOR BUART (Bluetooth Universal Asyncrhonous Receiver/Transmitter) aka UARTB #define UARTB_TXD_REG_ADDR (*(INT8U *) 0x40200000L) //TX REGISTER FOR UARTB SERIAL PORT #define UARTB_RXD_REG_ADDR (*(INT8U *) 0x40200000L) //RX REGISTER FOR UARTB SERIAL PORT #define UARTB_DIVISOR_LBYTE_REG_ADDR (*(INT8U *) 0x40200000L) //Lower byte for divisor when setting baud rate #define UARTB_DIVISOR_UBYTE_REG_ADDR (*(INT8U *) 0x40200004L) //Upper byte for divisor when setting baud rate #define UARTB_INT_CONTROL_REG_ADDR (*(INT32U *) 0x40200004L) //Interrupt enable register for FFUART (Value is 0x41 at start-up : DMA disabled ) #define UARTB_INT_ID_REG_ADDR (*(INT32U *) 0x40200008L) //READ ONLY - Contains interrupt code (Value is 0xC1 at start-up : FIFO mode enabled) #define UARTB_FCR_REG_ADDR (*(INT32U *) 0x40200008L) //WRITE ONLY - FIFO Enable/Reset registter for UARTB #define UARTB_LCR_REG_ADDR (*(INT32U *) 0x4020000CL) //Line control register. Contains DLAB bit that allows setting of baud #define UARTB_MCR_REG_ADDR (*(INT32U *) 0x40200010L) //Modem Control Register. This has an effect on whether interrupts are enabled or not #define UARTB_LINE_STATUS_REG_ADDR (*(INT32U *) 0x40200014L) //Line Status Register, used to control flow to the transmit FIFO #define UARTB_MSR_REG_ADDR (*(INT32U *) 0x40200018L) //Modem Status Register. Contains info on the handshaking lines #define UARTB_SCRATCH_PAD_REG_ADDR (*(INT32U *) 0x4020001CL) //Scratch pad register. Not used on chip #define UARTB_INFRARED_SELELCT_REG_ADDR (*(INT32U *) 0x40200020L) //Settings for infrared control register #define UARTB_RX_FIFO_OCCUPANCY_REG_ADDR (*(INT32U *) 0x40200024L) //Contains the number of characters in the receive FIFO (0-63) #define UARTB_ABR_REG_ADDR (*(INT32U *) 0x40200028L) //Auto-Baud Rate register. Contains bits for controlling baud rate generation #define UARTB_ABC_REG_ADDR (*(INT32U *) 0x4020002CL) //Auto-Baud Count register. Stores number of 14.857-MHz clock cycles used for AB //SERIAL PORT REGISTERS FOR SPI 1 (Used for the OEMV-1G GPS Receiver along with the GPIO58 Interrupt) #define SPI_SSCR0_1_REG_ADDR (*(INT32U *) 0x41000000L) //SSP 1 Control Register 0 (contains enable, clock rate, etc.) #define SPI_SSCR1_1_REG_ADDR (*(INT32U *) 0x41000004L) //SSP 1 Control Register 1 (contains clock direction, FIFO thresholds) #define SPI_SSSR_1_REG_ADDR (*(INT32U *) 0x41000008L) //SSP 1 Status Register contains errors and interrupts #define SPI_SSITR_1_REG_ADDR (*(INT32U *) 0x4100000CL) //SSP 1 Interrupt Test Register (Bits for testing interrupts) #define SPI_SSDR_1_REG_ADDR (*(INT32U *) 0x41000010L) //SSP 1 Data Write Register/Data Read Register //SERIAL PORT REGISTERS FOR SPI 2 (Used for the Cypress-IBIS-5-1300B Serial 3 wire interface) #define SPI_SSCR0_2_REG_ADDR (*(INT32U *) 0x41700000L) //SSP 2 Control Register 0 (contains enable, clock rate, etc.) #define SPI_SSCR1_2_REG_ADDR (*(INT32U *) 0x41700004L) //SSP 2 Control Register 1 (contains clock direction, FIFO thresholds) #define SPI_SSSR_2_REG_ADDR (*(INT32U *) 0x41700008L) //SSP 2 Status Register contains errors and interrupts #define SPI_SSITR_2_REG_ADDR (*(INT32U *) 0x4170000CL) //SSP 2 Interrupt Test Register (Bits for testing interrupts) #define SPI_SSDR_2_REG_ADDR (*(INT32U *) 0x41700010L) //SSP 2 Data Write Register/Data Read Register //SERIAL PORT REGISTERS FOR SPI 3 (I think this will be the main link to the Colony II Bus) #define SPI_SSCR0_3_REG_ADDR (*(INT32U *) 0x41900000L) //SSP 3 Control Register 0 (contains enable, clock rate, etc.) #define SPI_SSCR1_3_REG_ADDR (*(INT32U *) 0x41900004L) //SSP 3 Control Register 1 (contains clock direction, FIFO thresholds) #define SPI_SSSR_3_REG_ADDR (*(INT32U *) 0x41900008L) //SSP 3 Status Register contains errors and interrupts #define SPI_SSITR_3_REG_ADDR (*(INT32U *) 0x4190000CL) //SSP 3 Interrupt Test Register (Bits for testing interrupts) #define SPI_SSDR_3_REG_ADDR (*(INT32U *) 0x41900010L) //SSP 3 Data Write Register/Data Read Register //I2C REGISTERS FOR I2C INTERFACE #define I2C_IBMR_REG_ADDR (*(INT32U *) 0x40301680L) //I2C Bus Monitor Register #define I2C_IDBR_REG_ADDR (*(INT32U *) 0x40301688L) //I2C Data Buffer Register #define I2C_ICR_REG_ADDR (*(INT32U *) 0x40301690L) //I2C Control Register #define I2C_ISR_REG_ADDR (*(INT32U *) 0x40301698L) //I2C Status Register #define I2C_ISAR_REG_ADDR (*(INT32U *) 0x403016A0L) //I2C Slave Address Register //CLOCKS #define OS_OSCILLATOR_CONFIG_REG_ADDR (*(INT32U *) 0x41300008L) //Oscillator Configuration Register - this enables 13MHz and 32.768kHz oscillators #define CLOCK_ENABLE_REG_ADDR (*(INT32U *) 0x41300004L) //Clock enable register //OS TIMER #define OS_TIMER_MATCH1_REG_ADDR (*(INT32U *) 0x40A00004L) //OS Timer Match Register for OSMR1 #define OS_TIMER_STATUS_REG_ADDR (*(INT32U *) 0x40A00014L) //OS Timer Status Register (OSSR) (p. 1029 in PXA270 Manual) #define OS_TIMER_INT_ENABLE_REG_ADDR (*(INT32U *) 0x40A0001CL) //OS Timer Enable Register for 0-11 (bits 0-11) #define OS_TIMER_OSCR4_REG_ADDR (*(INT32U *) 0x40A00040L) //OS Timer Count Register for OS Timer 4 #define OS_TIMER_OSCR5_REG_ADDR (*(INT32U *) 0x40A00044L) //OS Timer Count Register for OS Timer 5 #define OS_TIMER_OSCR6_REG_ADDR (*(INT32U *) 0x40A00048L) //OS Timer Count Register for OS Timer 6 #define OS_TIMER_OSCR7_REG_ADDR (*(INT32U *) 0x40A0004CL) //OS Timer Count Register for OS Timer 7 #define OS_TIMER_OSCR8_REG_ADDR (*(INT32U *) 0x40A00050L) //OS Timer Count Register for OS Timer 8 #define OS_TIMER_OSCR9_REG_ADDR (*(INT32U *) 0x40A00054L) //OS Timer Count Register for OS Timer 9 #define OS_TIMER_OSCR10_REG_ADDR (*(INT32U *) 0x40A00058L) //OS Timer Count Register for OS Timer 10 #define OS_TIMER_OSCR11_REG_ADDR (*(INT32U *) 0x40A0005CL) //OS Timer Count Register for OS Timer 11 #define OS_TIMER_MATCH4_REG_ADDR (*(INT32U *) 0x40A00080L) //OS Timer Match Register for OS Timer 4 #define OS_TIMER_MATCH5_REG_ADDR (*(INT32U *) 0x40A00084L) //OS Timer Match Register for OS Timer 5 #define OS_TIMER_MATCH6_REG_ADDR (*(INT32U *) 0x40A00088L) //OS Timer Match Register for OS Timer 6 #define OS_TIMER_MATCH7_REG_ADDR (*(INT32U *) 0x40A0008CL) //OS Timer Match Register for OS Timer 7 #define OS_TIMER_MATCH8_REG_ADDR (*(INT32U *) 0x40A00090L) //OS Timer Match Register for OS Timer 8 #define OS_TIMER_MATCH9_REG_ADDR (*(INT32U *) 0x40A00094L) //OS Timer Match Register for OS Timer 9 #define OS_TIMER_MATCH10_REG_ADDR (*(INT32U *) 0x40A00098L) //OS Timer Match Register for OS Timer 10 #define OS_TIMER_MATCH11_REG_ADDR (*(INT32U *) 0x40A0009CL) //OS Timer Match Register for OS Timer 11 #define OS_TIMER_OMCR4_REG_ADDR (*(INT32U *) 0x40A000C0L) //OS Timer Match Control Register for OS Timer 4 #define OS_TIMER_OMCR5_REG_ADDR (*(INT32U *) 0x40A000C4L) //OS Timer Match Control Register for OS Timer 5 #define OS_TIMER_OMCR6_REG_ADDR (*(INT32U *) 0x40A000C8L) //OS Timer Match Control Register for OS Timer 6 #define OS_TIMER_OMCR7_REG_ADDR (*(INT32U *) 0x40A000CCL) //OS Timer Match Control Register for OS Timer 7 #define OS_TIMER_OMCR8_REG_ADDR (*(INT32U *) 0x40A000D0L) //OS Timer Match Control Register for OS Timer 8 #define OS_TIMER_OMCR9_REG_ADDR (*(INT32U *) 0x40A000D4L) //OS Timer Match Control Register for OS Timer 9 #define OS_TIMER_OMCR10_REG_ADDR (*(INT32U *) 0x40A000D8L) //OS Timer Match Control Register for OS Timer 10 #define OS_TIMER_OMCR11_REG_ADDR (*(INT32U *) 0x40A000DCL) //OS Timer Match Control Register for OS Timer 11 //INTERRUPT VECTORS #define BSP_UNDEF_INSTRUCTION_VECTOR_ADDR (*(INT32U *) 0xA0000004L) #define BSP_SWI_VECTOR_ADDR (*(INT32U *) 0xA0000008L) #define BSP_PREFETCH_ABORT_VECTOR_ADDR (*(INT32U *) 0xA000000CL) #define BSP_DATA_ABORT_VECTOR_ADDR (*(INT32U *) 0xA0000010L) #define BSP_IRQ_VECTOR_ADDR (*(INT32U *) 0xA0000018L) //Vector where the IRQs cause a jump to #define BSP_FIQ_VECTOR_ADDR (*(INT32U *) 0xA000001CL) //Vector where the FIQs cause a jump to #define BSP_IRQ_ISR_ADDR (*(INT32U *) 0xA0000038L) //This is the address where we'll store the IRQ_ISR function adddress #define BSP_FIQ_ISR_ADDR (*(INT32U *) 0xA000003CL) //This is the address where we'll store the FIQ_ISR function adddress //LED SPECIFIC ADDRESSES ON DEVELOPMENT BOARD #define MEMAP_BASE_SDRAM (0xA0000000) #define BOOTFLASH_PHYS_BASE (0x00000000) #define MEMAP_BASE_CPLD_FAST (0x08000000) #define CPLD_CE_REG_LED (MEMAP_BASE_CPLD_FAST + 0x30) #define CPLD_CE_REG_GPIO_DIR (MEMAP_BASE_CPLD_FAST + 0x30) #define CPLD_CE_CPLD_GPIO_1_OFF (0x10) #define CPLD_CE_GPIO_DATA_DIR_OUT (0x40) //ADDRESSES FOR THE SC16IS740 SPI-TO-UART CHIP #define SC16_DLL_ADDR 0x00 // Clock Divisor Low Byte (LCR[7] must be set) #define SC16_DLH_ADDR 0x01 // Clock Divisor High Byte (LCR[7] must be set) #define SC16_IER_ADDR 0x01 // Interrupt Enable Register (R/W) #define SC16_IIR_ADDR 0x02 // Interrupt Identification Register (Read Only) #define SC16_FCR_ADDR 0x02 // FIFO Control Register (Write Only) #define SC16_LCR_ADDR 0x03 // Line Control Register (R/W) #define SC16_MCR_ADDR 0x04 // Modem Control Register (R/W) #define SC16_LSR_ADDR 0x05 // Line Status Register (Read Only) #define SC16_MSR_ADDR 0x06 // Modem Status Register (Read Only) #define SC16_TCR_ADDR 0x06 // Transmission Control Register (R/W) Set MCR[2]=1 and EFR[4]=1 #define SC16_SPR_ADDR 0x07 // ScratchPad Register (R/W) #define SC16_TLR_ADDR 0x07 // Trigger Level Register (R/W) Set MCR[2]=1 and EFR[4]=1 #define SC16_TXLVL_ADDR 0x08 // TX FIFO Level Register (Read Only) #define SC16_RXLVL_ADDR 0x09 // RX FIFO Level Register (Read Only) #define SC16_IO_STATE_ADDR 0x0B // I/O state register (R/W) (Can latch values!) #define SC16_IO_INT_EN_ADDR 0x0C // Interrupt enable register (R/W) #define SC16_IO_CTRL_ADDR 0x0E // I/O control register (R/W) #define SC16_EFCR_ADDR 0x0F // Enhanced Feature Register //ADDRESSES FOR THE CYPRESS IBIS5-B-1300 CMOS SENSOR INTERNAL REGISTERS #define IBIS5_SEQUENCER_ADDR 0x00 // Control for Imager Sequencer, shutter type, etc. #define IBIS5_NROF_PIXELS_ADDR 0x01 // Number of pixels in a row to count #define IBIS5_NROF_LINES_ADDR 0x02 // Number of lines in a frame #define IBIS5_INT_TIME_ADDR 0x03 // Integration Time #define IBIS5_X_REG_ADDR 0x04 // X Start Position (default 0) #define IBIS5_YL_REG_ADDR 0x05 // Y-left Start Position (default 0) #define IBIS5_YR_REG_ADDR 0x06 // Y-Right Start Position (default 0) #define IBIS5_IMAGE_CORE_ADDR 0x07 // Image Core Register (Testing and swapping) #define IBIS5_AMPLIFIER_ADDR 0x08 // Amplifier Register (Controls gain) #define IBIS5_DACRAW_REG_ADDR 0x09 // Amplifier DAC raw offset (default 1000000) #define IBIS5_DACFINE_REG_ADDR 0x0A // Amplifier DAC fine offset (default 1000000) #define IBIS5_ADC_REGISTER 0x0B // ADC register (gamma correction, bit inversion) //I2C ADDRESSES #define I2C_MAX1239_SLAVE_ADDR 0x35 // I2C Slave Address for the MAX1239EEE chip //GPS SPECIFIC REGISTERS #ifdef USE_UARTB #define MARK1_GPS_GPIO_PIN 0x00001000; // GPIO 44 is MARK1 #else #define MARK1_GPS_GPIO_PIN 0x08000000; // GPIO 59 is MARK1 #endif /* ********************************************************************************************************* * OPERATORRS ********************************************************************************************************* */ #define REG32(base) (*((volatile unsigned int *)(base))) #define REG16(base) (*((volatile unsigned short *)(base))) #define REG8(base) (*((volatile unsigned char *)(base))) /* ********************************************************************************************************* * CONSTANTS ********************************************************************************************************* */ #define OS_TIMER_BIT_CLEAR 0xFFFFF010 /* ********************************************************************************************************* * FUNCTION PROTOTYPES ********************************************************************************************************* */ void BSP_Init(void); static void BSP_InitIntCtrl(void); INT32S putchar(INT32S c); INT32S ReadSC16Register(INT8U RegAddr, INT8U* RegValue); INT32S WriteSC16Register(INT8U RegAddr, INT8U RegValue); INT32S WriteIBIS5Register(INT8U RegAddr, INT16U RegValue); INT32S WriteI2C(INT8U SlaveAddr, INT8U Value); INT32S ReadI2C(INT8U SlaveAddr, INT16U* Result); void uart_pause(void); void cf_wait(void); void getTimeStamp(void); /* ********************************************************************************************************* * INTERRUPTS ********************************************************************************************************* */ //IRQ and FIQ handlers. These are located in bsp.c void BSP_IntDisAll(void); /********************************************************************************************************* * BITS *********************************************************************************************************/ #define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004 #define BIT3 0x00000008 #define BIT4 0x00000010 #define BIT5 0x00000020 #define BIT6 0x00000040 #define BIT7 0x00000080 #define BIT8 0x00000100 #define BIT9 0x00000200 #define BIT10 0x00000400 #define BIT11 0x00000800 #define BIT12 0x00001000 #define BIT13 0x00002000 #define BIT14 0x00004000 #define BIT15 0x00008000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000